Broad-band active delay line

ABSTRACT

A broad-band active delay line comprises a plurality of broad-band active delay cells configured in a cascade topology. Each broad-band active delay cell comprises a feedback loop and a feedforward path to achieve a high bandwidth.

RELATED APPLICATION

This application claims a continuation-in-part of U.S. application Ser.No. “12/421,647”, filed on Apr. 10, 2009, having the title “HIGH-SPEEDCONTINUOUS-TIME FIR FILTER”, having the same inventors, the contents ofwhich are incorporated herein by reference.

FIELD OF TECHNOLOGY

This disclosure relates generally to delay line, and in particularlyrelates to methods and apparatus of a broad-band active delay line.

BACKGROUND

A delay line is an apparatus for receiving an analog input signal andgenerating accordingly a plurality of output signals, wherein saidoutput signals are substantially similar to the input signal but aredelayed and uniformly displaced in time. For example, a particular delayline receives an analog input signal of 1 GHz and generating five outputsignals that are of the same frequency (1 GHz) but uniformly displacedin time with a spacing of 100 ps. A delay line usually employs aplurality of delay cells that are cascaded in sequence for generating aplurality of output signals, respectively. As long as said delay cellsare substantially identical, the output signals are substantiallysimilar but uniformly displaced in time. However, the delay cells arepractically limited in bandwidth, and therefore the time spacing in theoutput analog signal is frequency dependent. A broad-band delay cellmaintains substantially the same time spacing for signals ranging fromDC to a high frequency. A broad-band delay line usually employs aplurality of transmission lines or distributed L-C networks. For anintegrated circuit implementation, however, transmission lines anddistributed L-C networks both demand large circuit areas. An activedelay line employs transistors to achieve the function of delay. For anintegrated circuit implementation, an active delay line is usuallyhighly efficient in circuit area but the bandwidth is usually highlylimited without consuming a high power to drive up the circuit speed.What is needed is a power efficient broad-band active delay line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a functional block diagram of a broadband active delay cellin accordance with the present invention.

FIG. 2 shows an embodiment of a first summing amplifier suitable forused in the broadband active delay cell of FIG. 1.

FIG. 3A shows an embodiment of a second summing amplifier suitable forused in the broadband active delay cell of FIG. 2.

FIG. 3B shows an embodiment of a buffer circuit that can be incorporatedinto the second summing amplifier of FIG. 3A.

FIG. 4 shows a functional block diagram of a delay line.

SUMMARY OF INVENTION

In various embodiments, a delay cell is disclosed, the delay cellcomprising: a first summing amplifier for receiving an input signal andan output signal and for outputting an intermediate signal, and a secondsumming amplifier for receiving the input signal and the intermediatesignal and for outputting the output signal.

In various embodiments, a delay line is disclosed, the delay linecomprising a plurality of delay cells configured in a cascade topology,each of said delay cells comprising: a first summing amplifier forreceiving an input signal and an output signal and for outputting anintermediate signal, and a second summing amplifier for receiving theinput signal and the intermediate signal and for outputting the outputsignal.

In various embodiments, a delay cell is disclosed, the delay cellcomprising a negative feedback loop in conjunction with a feedforwardpath.

In various embodiments, a delay line is disclosed, the delay linecomprising a plurality of delay cells configured in a cascade topology,each of said delay cells comprising a negative feedback loop inconjunction with a feedforward path.

In various embodiments, a method for delaying an input signal isdisclosed, the method comprising: receiving the input signal and anoutput signal; performing a first weighted sum on the input signal andthe output signal to generate an intermediate signal; receiving theintermediate signal and the input signal; and performing a secondweighted sum on the intermediate signal and the input signal to generatethe output signal.

DETAILED DESCRIPTION The following detailed description refers to theaccompanying drawings which show, by way of illustration, variousembodiments in which the invention may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice these and other embodiments. The various embodiments are notnecessarily mutually exclusive, as some embodiments can be combined withone or more other embodiments to form new embodiments. The followingdetailed description is, therefore, not to be taken in a limiting sense.

In an embodiment depicted in FIG. 1, a delay cell 100 comprises: a firstsumming amplifier 121, which receives an input signal x and an outputsignal y and generates an intermediate signal z; and a second summingamplifier 122, which receives the input signal x and the intermediatesignal z and generates the output signal y. The first amplifier 121performs a weighted-sum function that can be mathematically modeled as:

Z(s)=(a ₁ ·X(s)+a ₂ ·Y(s))·G ₁(s)   (1)

where X(s), Y(s), and Z(s) denote the Laplace transforms of x, y, and,z, respectively, a₁ and a₂ are weights for the two summing inputs x andy, respectively, and G₁(s) is a frequency response of the first summingamplifier 121. The second amplifier 122 performs a weighted-sum functionthat can be mathematically modeled as:

Y(s)=(a ₃ ·X(s)+a ₄ ·Z(s))·G₂(s)   (2)

where a₃ and a₄ are weights for the two summing inputs x and z,respectively, and G₂(s) is a frequency response of the second summingamplifier 122. Combining Equations (1) and (2), one obtains:

Y(s)=X(s)·i [a₃ ·G ₂(s)+a ₁ ·a ₄ ·G ₁(s)·G ₂(s)]/[1−a ₂ ·a ₄ ·G ₁(s)·G₂(s)]  (3)

The transfer function of the delay cell 100 is:

H(s)=Y(s)/X(s)=[a ₃ ·G ₂(s)+a ₁ ·a ₄ ·G ₁(s)·G ₂(s)]/[1−a ₂ ·a ₄ ·G₁(s)·G ₂(s)]  (4)

In various embodiments: the G₁(s) and G₂(s) are both positive definitefunctions of s; a₁, a₃, and a₄ are all positive; and a₂ is negative. Inthese embodiments, the delay cell 100 comprises a negative feedback loopthat leads to the expression of the denominator of Equation (4). As wellknown in circuit design theory, a negative feedback is a usefultechnique to extend a bandwidth of a circuit. In addition, the delaycell 100 further comprises a feedforward path that leads to anadditional term a₃·G₂(s) in the numerator of Equation (4). Thefeedforward path is a fast path, because it effectively bypasses thefirst summing amplifier 121. Due to using a combination of the negativefeedback and the feedforward path, the delay cell 100 can have a highbandwidth.

An exemplary circuit 200 depicted in FIG. 2 is suitable for embodyingthe first summing amplifier 121 for the delay cell 100 of FIG. 1. Inthis embodiment, a differential circuit topology is used, wherein asignal is embodied by a positive-end signal (annotated by the subscript“+”) and a negative-end signal end (annotated by the subscript “−”). Forinstance, the signal x is represented by the positive-end signal x₊ andthe negative-end signal x⁻ and the signal x is equal to a differencebetween the positive-end signal x₊ and the negative-end signal x⁻.Circuit 200 comprises: a first differential pair comprised of two NMOS(n-channel metal-oxide semiconductor) transistors M₁₊ and M¹⁻, a seconddifferential pair comprised of two NMOS transistors M₂₊ and M²⁻, a firstcurrent source I₁, a second current source I₂, and a pair of resistorsR₁₊ and R¹⁻. Throughout this disclosure, V_(SS) denotes a firstvirtually fixed-potential circuit node that is usually referred to as“ground,” and V_(DD) denotes a second virtually fixed-potential circuitnode that is usually referred to as “supply.” The first differentialpair M₁₊-M¹⁻ is biased by the first current source I₁, receives andprovides amplification for the input signal x, and delivers anamplification output to the resistor pair R₁₊-R¹⁻, which serves as aload. The second differential pair M₂₊-M²⁻ is biased by the secondcurrent source I₂, receives and provides amplification for the outputsignal y, and also delivers an amplification output to the resistor pairR₁₊-R¹⁻. Since the resistor pair R₁₊-R¹⁻ is a shared load for the firstdifferential pair M₁₊-M¹⁻ and the second differential pair M₂₊-M²⁻, thetwo amplification outputs are effectively summed, resulting in theintermediate signal z. In this embodiment, with reference to Equation(1), the coefficient a₁ is a positive number determined by the size ofthe first differential pair M₁₊-M¹⁻ and the magnitude of the firstcurrent source I₁, while the coefficient a₂ is a negative numberdetermined by the size of the second differential pair M₂₊-M²⁻ and themagnitude of the second current source I₂.

An exemplary circuit 300 depicted in FIG. 3A is suitable for embodyingthe second summing amplifier 122 for the delay cell 100 of FIG. 1. Inthis embodiment, a differential circuit topology is also used. Circuit300 comprises: a first differential pair comprised of two NMOStransistors M₃₊ and M³⁻, a second differential pair comprised of twoNMOS transistors M₄₊ and M⁴⁻, a first current source I₃, a secondcurrent source I₄, and a pair of resistors R₂₊ and R²⁻. The firstdifferential pair M₃₊-M³⁻ is biased by the first current source I₃,receives and provides amplification for the input signal x, and deliversan amplification output to the resistor pair R₂₊-R²⁻, which serves as aload. The second differential pair M₄₊-M⁴⁻ is biased by the secondcurrent source I₄, receives and provides amplification for theintermediate signal z, and also delivers an amplification output to theresistor pair R₂₊-R²⁻. Since the resistor pair R₂₊-R²⁻ is a shared loadfor the first differential pair M₃₊-M³⁻ and the second differential pairM₄₊-M⁴⁻, the two amplification outputs are effectively summed, resultingin the output signal y. In this embodiment, with reference to Equation(2), the coefficient a₃ is a positive number determined by the size ofthe first differential pair M₃₊-M³⁻ and the magnitude of the firstcurrent source I₃, while the coefficient a₄ is a positive numberdetermined by the size of the second differential pair M₄₊-M⁴⁻ and themagnitude of the second current source I₄. In an alternative embodimentnot shown in figure, the intermediate signal z is not directly providedas input to the second differential pair M₄₊-M⁴⁻; instead, a buffercircuit 310 is used and inserted between the intermediate signal z fromthe first summing amplifier 121 and the second differential pair M₄₊-M⁴⁻of the second summing amplifier 122. As illustrated in an example shownin FIG. 3B, the buffer circuit 310 comprises a third differential pairM₅₊-M⁵⁻ for receiving the intermediate signal z, and outputting abuffered signal z′, which is then provided as input to the seconddifferential pair M₄₊-M⁴⁻. The buffer circuit 310 further comprises athird current source I₅ for providing a bias to the third differentialpair M₅₊-M⁵⁻. The buffer circuit further comprises another resistor pairR₃₊-R³⁻ provided as a load to the third differential pair M₅₊-M⁵⁻ forgenerating the buffered signal z′.

Note that circuit 200 of FIG. 2 and circuit 300 of FIG. 3 are shown byway of example but not limitation. Alternative embodiments can beemployed, as long as the functions described by Equations (1) and (2)are satisfied.

By way of example but not limitation, a 5-stage delay line 400 isdepicted in FIG. 4. The 5-stage delay line comprises five substantiallyidentical delay cells 401-405 configured in a cascade topology forreceiving an input signal x and generating five output signals y₁, y₂,y₃, and so on. The 5-stage delay line 400 further comprises a dummy load410 used as a termination for the last delay cell 405 so that all delaycells see substantially identical load impedance. Each delay cell is abroad-band active delay cell comprising a negative feedback loop and afeedforward path, exemplified by the delay cell 100 of FIG. 1.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. This application isintended to cover adaptations and variations of the embodimentsdiscussed herein. Various embodiments use permutations and/orcombinations of embodiments described herein. It is to be understoodthat the above description is intended to be illustrative, and notrestrictive, and that the phraseology or terminology employed herein isfor the purpose of description.

1. A circuit comprising: a first summing amplifier for receiving aninput signal and an output signal and for outputting an intermediatesignal, and a second summing amplifier for receiving the input signaland the intermediate signal and for outputting the output signal.
 2. Thecircuit of claim 1, wherein the first summing amplifier comprises twodifferential pairs for receiving the input signal and the output signal,respectively.
 3. The circuit of claim 2, wherein the two differentialpairs share a load coupled to the two differential pairs for generatingthe intermediate signal.
 4. The circuit of claim 3 further comprises twocurrent sources for providing a bias for the two differential pairs,respectively.
 5. The circuit of claim 1, wherein the second summingamplifier comprises two differential pairs for receiving the inputsignal and the intermediate signal, respectively.
 6. The circuit ofclaim 5 further comprising a common load for generating the outputsignal.
 7. The circuit of claim 2, wherein the second summing amplifiercomprises two differential pairs for receiving the input signal and theintermediate signal, respectively.
 8. The circuit of claim 1, whereinthe transfer function of the circuit isH(s)=Y(s)/X(s)=[a₃·G₂(s)+a₁·a₄·G₁(s)·G₂(s)]/[1−a₂·a₄·G₁(s)·G₂(s)], whereX(s), Y(s), and Z(s) denote the Laplace transforms of the input signal,the output signal, and the intermediate signal, respectively, a₁ and a₂are weights for two summing inputs of the first summing amplifier,respectively, a₃ and a₄ are weights for two summing inputs of the secondsumming amplifier, respectively, and G₁(s) and G₂(s) are a frequencyresponse of the first and the second summing amplifiers, respectively.9. The circuit of claim 8, wherein a₁, a₃, and a₄ are all positive anda₂ is negative.
 10. The circuit of claim 1, wherein the circuitcomprises a feedforward path.
 11. The circuit of claim 1, wherein thecircuit comprises a negative feedback.
 12. The circuit of claim 1,wherein the circuit comprises a negative feedback and a feedforwardpath.
 13. A circuit comprising a plurality of delay cells configured ina cascade topology, wherein: each of said delay cells comprises anegative feedback loop and a feedforward path to extend a frequencyrange of operation of the circuit.
 14. The circuit of claim 13, whereinthe negative feedback loop includes a first amplification stage and asecond amplification stage, an output of the second amplification stagebeing provided as an input to the first amplification stage.
 15. Thecircuit of claim 14, wherein the feedforward path includes the secondamplification stage.
 16. A method of delaying an input signal applied toa circuit, the method comprising: (a) receiving the input signal and anoutput signal; (b) performing a first weighted sum on the input signaland the output signal to generate an intermediate signal; and (c)receiving the intermediate signal and the input signal; and (d)performing a second weighted sum on the intermediate signal and theinput signal to generate the output signal.
 17. The method of claim 16,wherein step (a) further comprises using two first differential pairs ofthe circuit to receive the input signal and the output signal,respectively.
 18. The method of claim 17, wherein step (b) furthercomprises using a first load of the circuit for the two differentialpairs to perform the first weighted sum.
 19. The method of claim 16,wherein step (c) further comprises using two second differential pairsof the circuit to receive the input signal and the intermediate signal,respectively.
 20. The method of claim 19, wherein step (d) furthercomprises using a second load of the circuit to perform the secondweighted sum.
 21. The method of claim 16, wherein the circuit comprisesa negative feedback and a feedforward path.